ECE1388 - VLSI Design Methodology
Contacts
Professor: Dr. Roman Genov
Email: roman@eecg.utoronto.ca
Lectures
- ECE1388 L0 - Intro and Opportunities.pdf
- ECE1388 L1 - CMOS Review.pdf
- ECE1388 L2 - CMOS Layout.pdf
- ECE1388 L3 - CMOS Theory.pdf
- ECE1388 L4 - CMOS Non-Idealities.pdf
- ECE1388 L5 - DC and Transient.pdf
- ECE1388 L6 - Logical Effort.pdf
- ECE1388 L7 - Power.pdf
- ECE1388 L8 - Interconnect.pdf
- ECE1388 L9 - Packaging.pdf
- ECE1388 L10 - Combinational Logic.pdf
- ECE1388 L11 - Circuit Families.pdf
- ECE1388 L12 - Sequential Logic.pdf
- ECE1388 L13 - Memories 1.pdf
- ECE1388 L14 - Memories 2.pdf
- ECE1388 L15 - Design for Test.pdf