An Overview of Noise-Shaping SAR ADC - From Fundamentals to the Frontier

Notes

Delta-Sigma ADCs need a fast quantizer to perform oversampling, traditionally flash ADCs perform this role.

Framework

SAR ADC

Comparator and feedback DAC sample and quantize the input signal. SAR uses comparator output to successively determine $D_{out}$. Low resolution of SAR will leave a residual error ($V_{res}$) in the output.

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1. generally CDAC based SAR ADC is used, leaving a residual voltage on the CDAC
2. loop filters sample and process residue
3. filtered residue is summed back into the input

$E_s$ models sampling noise
$E_q$ models quantization error, comparator noise, and DAC settling error
$E_d$ models DAC nonlinearity and mismatch

$H_{EF}$ (Error-Feedback) and $H_{CIFF}$ (Cascaded-Integrator Feed-Forward) are loop filters

$E_{N1}$ and $E_{N2}$ model input-referred noise of filters

$z^{-1}$ models minimum delay of loop filters

In CIFF path, feedback signal is summed by comparator and not CDAC. Thus acts as an offset

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Loop Filter

Loop filter is more efficient than that of DT-DSM since only small residue needs to be processed.

1. filters residue
2. amplifies residue at some frequencies
3. sums output back to SAR

performance strategies

• Passive (filtering and summing)

  • only needs switches and capacitors
  • PVT robust, scaling friendly, energy efficient
  • low gain

• Active

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