Cadence - Verilog Analog and Mixed Signal Simulation

UofT Environment Setup

1. Ensure these are not being sourced, check the ~/.cshrc file.

source /CMC/tools/CSHRCs/Cadence.INCISIVE.15
source /CMC/tools/CSHRCs/Cadence.IUS.820

2. Run these commands in this exact order.

source /CMC/tools/CSHRCs/Cadence.IC617
source /CMC/tools/CSHRCs/Cadence.XCELIUM
setenv LD PRELOAD /usr/lib/x86_64-linux-gnu/libstdc++.so.6

3. Add these lines to cds.lib file of the PDK directory.

SOFTINCLUDE $AMSHOME/tools/affirma ams/etc/connect lib/cds.lib
DEFINE sample $CDSHOME/tools/dfII/samples/cdslib/sample

Cadence Simulation

1. Launch ADE-L from config view.
   • The window should say config at the top. If not, correct it from Setup > Design.
2. Open Setup -> Simulator/Directory/Host.
   1. Set Simulator: ams.
3. Open Simulation -> Netlister and Run Options.
   1. Set Netlist and Run Mode: 0SS-based netlister with xrun
   2. Check Run Options: All, All, Stimulate.
4. Open Setup -> Connect Rules.
   1. Change Supply value/Net from 1.8 to 1.
   2. Make sure first row is selected, then click Advanced Setup checkbox.
   3. Change tr to 10p.